Memory circuits, including those embedded in integrated circuits (ICs), are of various known types, including, but not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), read only memory (ROM), and other non-volatile memories such as flash memory, phase-change memory (PCM), one-time-programmable (OTP) memory, and few-time-programmable (FTP) memory. Memory circuits typically comprise an array of memory storage cells, sometimes having as many as tens of millions of memory cells or more (e.g., megabits of storage).
Regardless of memory type, variations often occur within memory circuits, generally between otherwise identical memory cells in a memory array. Defective memory cells can also occur. Statistically, the larger the number of memory cells in the memory array, the wider the variations in characteristics (e.g., delay, power consumption, refresh rate, etc.) between the memory cells and the greater the number of defective memory cells there are. Such variations and/or defects in a memory circuit may result in some memory cells taking longer to read or write than other cells, or some memory cells requiring higher voltage or power to read or write than other cells. These memory cells are often referred to as weak cells or weak bits.
Conventionally, a memory circuit can accommodate weak cells by designing the entire memory circuit for worse-case memory cell operation, typically by setting memory operating timing, voltage, power and other parameters to provide correct functioning of weak cells. Unfortunately, however, setting memory circuit operational parameters to accommodate all memory cells, including weak cells, has a disadvantage of degrading performance of the majority of memory cells in the memory circuit, and using higher operating voltage than is necessary for proper functioning of the majority of memory cells undesirably increases power consumption in the memory circuit.
Alternatively, or additionally, memory circuits are known to employ redundant memory cells. To avoid tailoring operating parameters for all memory cells in a memory circuit based upon weak cell characteristics, the weak cells are replaced by corresponding redundant memory cells. However, replacement of weak cells by redundant cells in a memory circuit undesirably increases the physical size of the memory circuit and, moreover, can degrade performance of the circuit. Furthermore, there are typically substantial costs associated with implementing a redundancy methodology for replacing weak cells by spare cells, including, for example, increased testing, increased overhead circuitry required for cell replacement (e.g., circuitry for blowing fuses), etc.